1) Field of the Invention
The present invention relates to a method and an apparatus for designing a layout for large scale integrated (LSI) chips having a boundary scan register, and a computer product.
2) Description of the Related Art
Conventionally, a boundary scan register is not placed beforehand on an LSI chip, but is placed adjacent to either of an input/output (I/O) cell and a functional core cell, based on a wiring status with the I/O cell or the functional core cell through which a signal propagates (see, for example, Japanese Patent Application Laid-open No. 2002-26129).
However, since the boundary scan register should be built in a circuit of input data at the time of layout designing, it is necessary to insert the boundary scan register using a test synthesis tool before the layout designing.
When inserting the boundary scan register, the boundary scan register is placed adjacent to either of the I/O cell and the functional core cell based on the wiring status with the I/O cell or the functional core cell, so as to shorten the wiring, to prevent degradation of the circuit from the signal propagation, such as a timing error due to wiring delay. Therefore, since it is necessary to-strictly extract a placement area of the boundary scan register, much time is required until the boundary scan register can be placed at an optimum position, resulting in a long time to design the layout.